Joules RTL Power Solution
Accurately measure and reduce power consumption
during RTL design exploration


Deliver 20X Faster Time-Based RTL Power Analysis

Getting an accurate measure of RTL power consumption during design exploration has long been a major challenge for SoC design teams. System-level verification tools have the capacity to exercise real use cases, but they are disconnected from the implementation tools that translate RTL to gates and wires and from signoff tools that validate the final design.

Cadence Joules RTL Power Solution closes this gap by delivering time-based RTL power analysis with system-level runtimes and capacity while still providing high-quality estimates of gates and wires.

Built on a multi-threaded frame-based architecture, the Joules RTL Power Solution delivers 20X faster time-based RTL power analysis as compared to other methods. The tool also incorporates rapid prototype technology from the Cadence Genus Synthesis Solution that can analyze designs of up to 20 million instances overnight with gate-level accuracy of within 15% of signoff. In addition, the Joules RTL Power Solution integrates seamlessly with the Cadence Palladium Accelerator/Emulator for early system-level power analysis and optimization.


Delivers Unmatched Power Reductions
in RTL and During Implementation
Power Accuracy

RTL power estimates within 15% of signoff, including glitch power from RTL stimulus


Up to 20X faster time-based power analysis, with unique ideal power-guided RTL power reduction methodology

Verification Integration

Direct integration with Palladium and Xcelium platforms for power analysis of workloads, identifying critical windows of interest

Implementation Integration

Native integration inside Innovus, Genus, and Stratus HLS technologies for automatic power optimization

상호명 : 뉴링크테크놀로지│대표 : 유영태│대표전화 : 02-508-0232

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COPYRIGHTⓒ뉴링크테크놀로지.All rights reserved

상호명 : 뉴링크테크놀로지│대표 : 유영태│대표전화 : 02-508-0232

주소 : 서울특별시 송파구 법원로 127 문정대명벨리온 1106호│E-Mail :

COPYRIGHTⓒ뉴링크테크놀로지.All rights reserved