• Production-proven over thousands of tapeouts
• Reduced debug time with powerful and intuitive, interactive debugging solutions
• In-memory integration with Virtuoso environment reduces full-chip verification iterations and improves productivity

With PVS, you can complete advanced-node design signoff checks (DRC and LVS) with peace of mind. Foundries provide the PVS rule decks, and PVS provides efficient, comprehensive debug tools to reduce debug time and increase productivity. This solution supports advanced process node technologies (such as double patterning, triple patterning, quadruple patterning, 3D-IC, FinFET rules,   advanced device extraction, and more), and it extends physical verification  technology into design reliability checking and constraint validation. PVS also offers a distributed processing capability that greatly accelerates throughput without requiring specialized hardware.