OVERVIEW

Industry’s Fastest Adopted and Trusted Signoff 

Solution for FinFET Designs

The Cadence Tempus Timing Solution is the industry’s most trusted static timing analysis (STA) tool for FinFET designs. It is the fastest STA tool in the industry, providing faster design closure turnaround time while delivering the best-in-its-class power, performance, and area (PPA). Customers trust innovative Tempus capabilities such as SmartScope, CMMMC, Design Robustness Analysis, SmartMMMC Optimization, etc. to optimize and signoff their most complex, large, and complicated designs at advanced nodes.

The Tempus solution is deeply integrated with Cadence’s Innovus Implementation System, Quantus Extraction Solution, and Voltus IC Power Solution to deliver the best user experience during the entire design cycle.