OVERVIEW
Cadence Xcelium Logic Simulator provides best-in-class core engine performance for SystemVerilog, VHDL, SystemC®, e, UVM, mixed-signal, low power, and X-propagation. It leverages a set of domain-specific apps, including mixed-signal, machine learning-based test compression, and functional safety, that enable design teams to achieve verification closure early for IP and SoC designs.
KEY BENEFITS
Support for SystemVerilog, VHDL, SystemC, e, UVM, and IEEE UPF standards
Automated parallel and incremental build technologies to support the compilation of big SoC designs and best-in-class simulation engines for best regression throughput, including a multi-core engine to speed-up long-running test cases
Xcelium Apps such as mixed-signal, machine learning-based test compression, and functional safety for ease of mixing and matching different technologies needed throughout the design and verification cycles
상호명 : 뉴링크테크놀로지│대표 : 유영태│대표전화 : 02-508-0232
주소 : 서울특별시 송파구 법원로 127 문정대명벨리온 1106호
E-Mail : newlinktek@newlinktek.com
COPYRIGHTⓒ뉴링크테크놀로지.All rights reserved
상호명 : 뉴링크테크놀로지│대표 : 유영태│대표전화 : 02-508-0232
주소 : 서울특별시 송파구 법원로 127 문정대명벨리온 1106호│E-Mail : newlinktek@newlinktek.com
COPYRIGHTⓒ뉴링크테크놀로지.All rights reserved